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S5K437CX (1/4" vga cmos image sensor) data sheet revision 1.1

document title 1/4" optical size 640 480 (vga) 2.8v cmos image sensor revision history revision no. history draft date remark 0.0 initial draft mar, 01. 2004 1.0 changed the operation frequency (30mhz 24.54mhz). added the shutter operation range limit. added recommended value for selection of ob_area. added chip pad description. may, 18. 2004 1.1 added ac characteristic timing diagram (include standby timing diagram) july, 15. 2004
table of contents introduc tion ................................................................................................................... ..............................................2 featur es ....................................................................................................................... ...............................................2 produc ts ....................................................................................................................... ...............................................2 block di agram.................................................................................................................. ...........................................3 pixel a rray.................................................................................................................... ...............................................4 chip pad conf igurat ion......................................................................................................... ......................................5 chip pad de scription ........................................................................................................... .......................................6 package pin configuration (48 clcc, te st only) ................................................................................. ....................7 package pin description ( 48clcc, test only) .................................................................................... ......................8 maximum absolu te limit ......................................................................................................... ....................................9 electrical char acterist ics ..................................................................................................... ..................................10 control r egisters .............................................................................................................. ........................................13 operation de scription .......................................................................................................... .....................................18 timing c hart................................................................................................................... ...........................................25 vertical ti ming di agram ........................................................................................................ ................................25 48clcc package dimens ion (test only) ........................................................................................... .....................29
list of figures figure title page number number figure 1. bl ock di agram ........................................................................................................ ..................................... 3 figure 2. pixel arra y configur ation............................................................................................ ................................. 4 figure 3. pin c onfiguration.................................................................................................... ..................................... 7 figure 4. woi definit ion ....................................................................................................... ..................................... 18 figure 5. bayer space sub-sampling examples .................................................................................... ................. 19 figure 6. relati ve channel gain ................................................................................................ .............................. 20 figure 7. relati ve global gain ................................................................................................. ................................ 21 figure 8. recommended minimum gl obal gain cont rol value ........................................................................ ....... 21 figure 9. quadrisectional global gain control.................................................................................. ....................... 22 figure 10. i 2 c bus write cycle .............................................................................................................. ................... 23 figure 11. i 2 c bus read cycle............................................................................................................... .................. 24
1/4 inch vga cmos image sensor S5K437CX 2 introduction S5K437CX is a highly integrated single chip cmos image sensor developed by samsung with the 0.35 m cmos image sensor process technology . it is designed to implement high-e fficient and low-power photo sensor in the imaging application. the sensor has 640 x 480 effectiv e pixels with 1/4 inch optical format. the sensor digitizes the pixel output with the on-chip 10-bit adc bl ocks and drastically fixed pattern noise (fpn) with the on- chip cds. with the interface signals and 10-bit raw data dire ctly connected to the exter nal devices, you can easily set up the camera system. S5K437CX is suitable for lo w power camera module with 2.8v power supply. features ? process technology: 0.35 m dptm cmos ? optical size: 1/4 inch ? unit pixel: 5.6 m x 5.6 m ? effective resolution: 640x480, vga ? line progressive read out. ? 10-bit raw image data output ? programmable exposure time ? programmable gain control ? auto dark level compensation ? windowing and panning ? sub-sampling (2x, 3x, 4x) ? standby-mode for power saving ? maximum 30 frame per second ? bad pixel replacement ? single power supply voltage: 2.8v ? package type: 48-clcc (test only) products product code power supply backend process description S5K437CX01 2.8 v none monochrome image sensor S5K437CX02 2.8 v on-chip micro lens high sensitivity monochrome image sensor S5K437CX03 2.8 v on-chip color filter and micro lens rgb color image sensor
1/4 inch vga cmos image sensor S5K437CX 3 block diagram rstn stbyn mclk vsync hsync dclk scl sda strb vddd vssd vddio vssio vdda vssa data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 main clock divider timing generator control registers i 2 c interface 10-bit column adc odd column cds row driver active pixel sensor array even column cds 10-bit column adc post processing figure 1. block diagram
1/4 inch vga cmos image sensor S5K437CX 4 pixel array (top view on chip. displayed image will be flipped.) (14,14) read out start point active pixels optical black pixels (10,0) default window of interest 640x480 4 8 6 4 g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g g b g b g b r g r g r g 8 6 figure 2. pixel array configuration
1/4 inch vga cmos image sensor S5K437CX 5 chip pad configuration (0,0) 6 chip id effective pixel area (640x480) 13 14 23 24 28 29 33 513834
1/4 inch vga cmos image sensor S5K437CX 6 chip pad description pin no i/o name function vddd (18) power digital power for logical circuit ( vdd 10% ) vssd (1) power supply 0v (gnd) vddio (19,28) power i/o power supply for i/o circuit ( vdd 10% ) vssio (29,38) power 0v (gnd) vdda (4,15,27,30) power analog power supply for analog circuit ( vdd 10% ) vssa (2,3,16,17,25,26,31 ,32) power 0v (gnd) mclk (37) i master clock master clo ck pulse input for all timing generators. rstn (34) i reset initializing all the device register s. (active low) stbyn (33) i standby activating power saving mode. (high = normal operation, low = power saving mode) data0~data9 (5~14) o image data output 10-bit image data out puts. when adc resolution is reduced, the unused lower bits are set to 0. dclk (20) o data clock image data output synchronizing pulse output. hsync (21) o horizontal sync clock horizontal sy nchronizing pulse or data valid signal output. vsync (22) o vertical sync clock vertical synchronizing pulse or line valid signal output. scl (36) i serial interface clock i2c serial interface clock input sda (35) i/o serial interface data i2c serial interface data bus (external pull-up resistor required) test1 (23) i test input 1 test input signal. though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. test2 (24) i test input 2 test input signal. though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
1/4 inch vga cmos image sensor S5K437CX 7 package pin configuration (48 clcc, test only) 19 20 21 22 23 24 25 26 27 28 29 30 (nc (nc) data8 data7 data6 data5 data4 data3 data2 data1 (nc) (nc) stbyn vssa vssa vdda vssio (nc) (nc) vddio vdda vssa vssa test2 data0 (nc) vdda vssa vssa vssd (nc) vssio mclk scl sda rstn data9 (nc) vdda vssa vssa vddd (nc) vddio dclk hsync vsync test1 first readout pixel 7 8 9 10 11 12 13 14 15 16 17 18 31 32 33 34 35 36 37 38 39 40 41 42 6 5 4 3 2 1 48 47 46 45 44 43 figure 3. pin configuration
1/4 inch vga cmos image sensor S5K437CX 8 package pin description (48clcc, test only) pin no i/o name function vddd (24) power digital power supply for logical circuit ( v dd 10% ) vssd (1) power 0v (gnd) vddio (26,35) power i/o power supply for i/o circuit ( v dd 10% ) vssio (38,47) power 0v (gnd) vdda (4,21,34,39) power analog power supply for analog circuit ( v dd 10% ) vssa (2,3,22,23,32,33,40 ,41) power 0v (gnd) mclk (46) i master clock master clo ck pulse input for all timing generators. rstn (43) i reset initializing all the device register s. (active low) stbyn (42) i standby activating power saving mode. ( high=normal operation, low=power saving mode ) data0~data9 (6,9 ~ 16,19) o image data output 10-bit image data out puts. when adc resolution is reduced, the unused lower bits are set to 0. dclk (27) o data clock image data output synchronizing pulse output. hsync (28) o horizontal sync clock horizontal sy nchronizing pulse or data valid signal output. vsync (29) o vertical sync clock vertical synchronizing pulse or line valid signal output. scl (45) i serial interface clock i2c serial interface clock input sda (44) i/o serial interface data i2c serial interface data bus (external pull-up resistor required) test1 (30) i test input 1 test input signal. though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. test2 (31) i test input 2 test input signal. though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
1/4 inch vga cmos image sensor S5K437CX 9 maximum absolute limit characteristic symbol value unit operating voltage (vddd, vddio, vdda supply related to vssd, vssio, vssa, vbba) v dd -0.3 to 3.8 v input voltage v in -0.3 to v dd +0.3 (max. 3.8) operating temperature t opr -20 to +60 c storage temperature t stg -40 to +125(1) -40 to +85(2) notes: 1. storage temperature tole rance for s5k437c(l)x01. 2. storage temperature tolerance fo r s5k437c(l)x02 and s5k437c(l)x03.
1/4 inch vga cmos image sensor S5K437CX 10 electrical characteristics dc characteristics (t a = -20 to +60 c, c l = 15pf) characteristics symbol condition min typ max unit operating voltage v dd vddd, vddio, vdda 2.55 2.8 3.05 v input voltage (1) v ih - 0.8v dd - - v il - 0 - 0.2v dd input leakage current (2) i il v in = v dd to v ss -10 - 10 a input leakage current with pull-down (3) i ild v in = v dd 10 30 60 high level output voltage (4) v oh i oh = -1 a v dd - 0.05 - - v i oh = -4ma 2.4 - - low level output v ol i ol = 1 a - - 0.05 voltage (5) i ol = 4ma - - 0.4 high-z output leakage current (6) i oz v out = v dd - - 10 a supply current i stb stbyn = low(active) all input clocks = low - - 10 a i dd f mclk = 24.54mhz v dd = 2.8v - 18 - ma 0 lux illumination notes: 1. applied to mclk, rstn, stbyn, strb, scl, sda, test1, test2 pin. 2. mclk, rstn, stbyn, strb, scl, sda pin 3. test1, test2 pin 4. dclk, hsync, vsync, data0 to data9 pin 5. dclk, hsync, vsync, data0 to data9, scl, sda pin 6. sda pin when in high-z output state
1/4 inch vga cmos image sensor S5K437CX 11 imaging characteristics (light source with 3200k of color temperature and ir cut filter (cm-500s, 1mm th ickness) are used. it is recommended that the sensor should operate in compliance to the following typical values. the control registers are set to the default values. t a = 25 c unless otherwise specified.) characteristics symbol condition min typ max unit saturation level (1) v sat S5K437CX 850 900 - mv sensitivity (2) s S5K437CX01 - 1500 - mv/ S5K437CX02 - 4000 - lux sec S5K437CX03 - 1500 - dark level (3) v dark t a = 40 c - 9 18 mv/sec t a = 60 c - 50 100 dynamic range (4) dr - 60 - db signal to noise ratio (5) s/n - 40 - dark signal non- uniformity (6) dsnu t a = 60 c - - 100 mv/sec photo response non- uniformity (7) prnu - 4 8 % vertical fixed pattern noise (8) vfpn 4 8 % horizontal fixed pattern noise (9) hfpn 4 8 % notes: 1. minimum output level measured at 100 lu x illumination for exposure time 1/30 sec. 7x7 rank filter is applied to the whole pixel area to eliminate the values from defective pixels. 2. average output measured at 25% of saturation level illumination for ex posure time 1/30 sec. green channel output values are used for color version. 3. average output measur ed at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark leve l rms noise excluding fixed pattern noise ). 60db is limited by 10-bit adc. 5. 20 log (average output level/rms noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. difference between maximum and minimum pixel output levels at zero illumination for ex posure time 1/30 sec. 7x7 median filter is applied to the whole pixel area to eliminate the values from defective pixels. 7, difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level illumination for exposure time 1/30 se c. 7x7 median filter is applied to the w hole pixel area to eliminate the values from defective pixels. 8. for the column-averaged pixel output values, maximum relati ve deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. for the row-averaged pixel output values, maximum relative deviation of values from 7-dept h median filtered values for neighboring 7 columns at 25% of saturation le vel illumination for exposure time 1/30 sec.
1/4 inch vga cmos image sensor S5K437CX 12 ac characteristics (v dd = 2.55v to 3.05v for S5K437CX, ta = -20 to + 60 c, c l = 50pf) characteristic symbol condition min typ max unit main input clock frequency f mclk duty = 50% 4 (1) 12 24.54 (3) mhz data output clock frequency f dclk - 2 6 12.27 propagation delay time t pdmv vsync output - - 20 ns from main input clock t pdmh hsync output - - 20 t pdmd dclk output - - 15 t pdmo data output - - 20 propagation delay time t pddv vsync output - - 10 from data output clock t pddh hsync output - - 5 t pddo data output - - 5 reset input pulse width t wrst rstn = low (active) 5 - - t mclk (2) standby input pulse width t wstb stbyn = low (active) 4 - - notes: 1. 8-bit adc resolution case. if 10-bit adc resolu tion is used, the frequency should be over 12mhz. 2. the period time of main input clock, mclk. t pdmd data mclk dclk 0.5v dd hsync vsync t pddo t pdmo t pdmd t pddh t pdmh t pddh t pdmh t pddv t pdmv
1/4 inch vga cmos image sensor S5K437CX 13 i 2 c serial interface characteristics characteristic symbol condition min typ max unit clock frequency f sck - - - 400 khz clock high pulse width t wh sck 800 - - ns clock low pulse width t wl sck 1000 - - clock rise/fall time t r /t f sck, sda - - 300 data set-up time t ds sda to sck 300 - - data hold time t dh sda to sck 1200 - - start condition hold time t sth - 4 t mclk stop condition setup time t sts - 4 - - stop to new start gap t gss - 8 - - capacitance for each pin c pin scl, sda - - 4 pf capacitive bus load c bus scl, sda - - 200 pull-up resistor r pu scl, sda to v dd 1.5 - 10 k ? rstn stbyn t wstb t wrst mclk system reset partial power down complete power down
1/4 inch vga cmos image sensor S5K437CX 14 control registers addres s (hex) reset value bits mnemonic description 00h 02h [5] bprm bad pixel replacement mode 0b: disabled (default), 1b: enabled [4] not use [3] ccsm color channel separation mode 0b: not separated (default), 1b: separated [2] shutc electronic shutter mode 0b: disabled (default), 1b: enabled [1:0] adcres adc resolution 00b: 8-bit, 01b: 9-bit, 10b: 10-bit (default) 01h 10h [7] mircv vertical mirror control 0b: normal (default), 1b: mirrored [6] mirch horizontal mirror control 0b: normal (default), 1b: mirrored [5:4] mcdiv main clock divider 00b: dclk=mclk, 01b: dclk=mclk 2 (default) 10b: dclk=mclk 4, 11b: dclk=mclk 8 [3:2] subsr row subsampling mode 00b: disabled (default), 01b: 2x, 10b: 3x, 11b: 4x [1:0] subsc column subsampling mode 00b: disabled (default), 01b: 2x, 10b: 3x, 11b: 4x 02h 00h [0] wrp_high row start point for window of interest 03h 0eh [7:0] wrp_low wrp[8:0] = 14d(default) 04h 00h [0] wcp_high column start point for window of interest 05h 0eh [7:0] wcp_low wcp[8:0] = 14d(default) 06h 01h [0] wrd_high row depth for window of interest 07h e0h [7:0] wrd_low wrd[8:0] = 480d(default) 08h 02h [1:0] wcw_high column width for window of interest 09h 80h [7:0] wcw_low wcw[9:0] = 640d(default) 0ah 80h [7:0] (factory use only)
1/4 inch vga cmos image sensor S5K437CX 15 addres s (hex) reset value bits mnemonic description 0dh 01h [4:0] cintr_high row-step integration time in continuous frame capture mode (range is described in operation description) 0eh 06h [7:0] cintr_low cintr[12:0] = 262d (default) 0fh 00h [5:0] cintc_high column-step integration time in continuous frame capture mode (range is described in operation description) 10h 00h [7:0] cintc_low cintc[13:0] = 0d (default) 11h 01h [7:0] vswd vsync width vswd[7:0] = 1d (default) 12h 00h [5] vspolar vsync polarity 0: active high (default), 1: active low [4] vsdisp vsync display mode 0: sync mode (default), 1: data valid mode [1:0] vsstrt_high vsync start position vsstrt[9:0] = 0d (default) 13h 00h [7:0] vsstrt_low 14h 00h [4:0] vblank_high vertical blank depth vblank[12:0] = 45d (default) 15h 2dh [7:0] vblank_low 16h 20h [7:0] hswd hsync width hswd[7:0] = 32d (default) 17h 00h [5] hspolar hsync polarity 0: active high (default), 1: active low [4] hsdisp hsync display mode 0: sync mode (default), 1: data valid mode [1:0] hsstart_high hsync start position 18h 00h [7:0] hsstart_low hsstrt[9:0] = 0d (default) 19h 00h [5:0] hblank_high horizontal blank depth 1ah 8ch [7:0] hblank_low hblank[13:0] = 140d (default)
1/4 inch vga cmos image sensor S5K437CX 16 addres s (hex) reset value bits mnemonic description 1bh 77h [3:0] sgg1 1 st quadrisectional global gain 7d (default) [7:4] sgg2 2 nd quadrisectional global gain 7d (default) 1ch 77h [3:0] sgg3 3 rd quadrisectional global gain 15d (default) [7:4] sgg4 4 th quadrisectional global gain 15d (default) 1dh 00h [6:0] pgcr red channel gain pgcr[6:0] = 0d (default) 1eh 00h [6:0] pgcg1 green(red row) channel gain or all channel gain ( ccsm = 0) pgcg1[6:0] = 0d (default) 1fh 00h [6:0] pgcg2 green(blue row) channel gain pgcg2[6:0] = 0d (default) 20h 00h [6:0] pgcb blue channel gain pgcb[6:0] = 0d (default) 21h 80h [7:0] offsr red channel analog offset offsr[7:0] = 128 (default) 22h 80h [7:0] offsg1 green(red row) channel analog offset or all channel offset ( ccsm =0) offsg1[7:0] = 128 (default) 23h 80h [7:0] offsg2 green(blue row) channel analog offset offsg2[7:0] = 128 (default) 24h 80h [7:0] offsb blue channel analog offset offsb[7:0] = 128 (default) 25h 14h [6:0] pthresh bad pixel threshold pthresh[6:0] = 20d (default) 26h 00h [7:0] adcoffs adc offset adcoffs[7:0] = 0d (default)
1/4 inch vga cmos image sensor S5K437CX 17 addres s (hex) reset value bits mnemonic description 27h 0ch [5] (factory use only) [4] not use [3:0] (factory use only) 28h 40h [7:5] (factory use only) [4:0] (factory use only) 29h 00h [7:0] (factory use only) 2ah 00h [7:0] blank blank register for general purpose 2bh 02h [7:6] (factory use only) [5] (factory use only) [4] (factory use only) [3] (factory use only) [2] (factory use only) [1] (factory use only) [0] (factory use only) 2ch 00h [7] adlc_mod_d adlc mode always enable when 0b: disabled (default), 1b: enabled [6] adlc_mod_c adlc mode works when gain value is changed 0b: disabled (default), 1b: enabled [5] adlc_mod_b adlc mode works when shutter value is changed 0b: disabled (default), 1b: enabled [4] adlc_mod_a adlc mode works till adlc length value 0b: disabled (default), 1b: enabled [3:2] feedback_gain_b feedback gain value about adlc adlc formula : dnew = a*(obold + obnew) + b*dold 00b : 0 (default), 01b : 0.5, 10b : 0.75, 11b : 1 [1:0] feedback_gain_a feedback gain value about adlc 00b : 0 (default), 01b : 0.5, 10b : 0.25, 11b : 0.125
1/4 inch vga cmos image sensor S5K437CX 18 addres s (hex) reset value bits mnemonic description 2dh 10h [7] mckout_en dck pad control 0b : stable value (default), 1b : output enable [6] b2 i/o driver fan-out control register. [5] b1 {b2, b1, b0} = {001} (1/3), {011} (2/3), [4] b0 {111} (3/3) [3] ob_sel adlc formura : dnew = a*(obold + obnew) + b*dold 0b : obold = obold (default) 1b : obold = obnew [2] ob_area ob area selection 0b : 128 * 8 (default), 1b : 512*2 (recommend) [1:0] adlc_length adlc function works only during this value when adlc_mod_a enabled, 00b : 1 frame, 01b : 2 frames, 10b : 3 frames, 11b : 4 frames 2eh cch [7:4] (factory use only) [3:0] (factory use only) 2f 0ch [4] tg_sel pixel tg signal selection 0b: disabled (default), 1b: enabled [3:0] (factory use only
1/4 inch vga cmos image sensor S5K437CX 19 operation description 1. output data format 1-1. main clock divider all the data output and sync signals are synchronized to data clock output ( dclk ). it is generated as the main clock input ( mclk ) is divided. the dividing ratio is 1, 2, 4, and 8 according to main clock dividing control register ( mcdiv ). for 10-bit adc and vga resolution, dividing ratio of mo re than 2 is required. if ratio of 1 is used, the duty must be within 40% to 60%. 1-2. synchronous signal output the horizontal sync ( hsync ) and vertical sync ( vsync ) signals are also available. t he sync pulse width, polarity and position are programmable on the control registers (re f. timing chart). when display mode is activated, the sync signal outputs indicate t hat the output data is valid ( hsdisp = 1) or the output rows are valid ( vsdisp = 1). 1-3. window of interest control window of interest (woi) is defined as the pixe l address range to be read out. the woi can be assigned anywhere on the pixel array. it is compos ed of four values: row start pointer ( wrp ), column start pointer ( wcp ), row depth( wrd ) and column width ( wcw ). each value can be programmed on the control registers. for convenience of color signal processing, wcp is truncated to even numbers so that the starting data of each line is on the red and green column of bayer pattern. figure 4 illustrates the woi on the displayed pixel image. window of interest (wcp,wrp) wcw wrd 0 687 507 figure 4. woi definition 1-4. vertical mirror and horizontal mirror mode control the pixel data are normally read out from left to right in horizontal direction and from top to bottom in vertical direction. by changing the mirror mode, the read-out sequence can be reversed and the resulting image can be flipped like a mirror image. pixel data are read out from ri ght to left in horizontal mirror mode and from bottom to top in vertical mirror mode. the horizontal and the ve rtical mirror mode can be programmed on the horizontal mirror control register ( mirch ) and vertical mirror control register ( mircv ). 1-5. sub-sampling control the pixel data in sub-sampling rate can be read out in bot h horizontal and vertical direction. sub-sampling can be done in four rates : full, 1/2, 1/3 and 1/4. you can control the sub-sampling on the sub-sampling control registers, subsr and subsc . the sub-sampling is performed only in the bayer space.
1/4 inch vga cmos image sensor S5K437CX 20 r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b subsr = 00b, subsc = 11b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b r g g b subsr = 01b, subsc = 01b figure 5. bayer space sub-sampling examples 1-6. line rate and frame rate control (virtual frame) the line rate and the frame rate vary depending on the size of virtual frame. the virtual frame width and depth are controlled to effective woi and blank depths. the effectiv e woi is scaled by the subsampling factors from woi set by register values. for cds and adc function, the virtual column width must be larger than (adcres+1)*256/(2^mcdiv)+ 110, where adcres is the adc resolution cont rol register value. the resulting frame time and line time which are inverse of frame rate and line rate are represented by following equations: 1 frame time = { wrd / (subsr+1) + vblank } * (1 line time) 1 line time = { wcw / (subsc+1) + hblank } * ( dclk period) 1-7. continuous frame capture mode(cfcm) integrat ion time control (electronic shutter control) in cfcm operation, the integration time is controll ed by shutter operation. the shutter operation is done when shutter control register ( shutc ) is set to '1'. in shutter operation, the integration time is determined by the row step integration time control register( cintr ) and column step integration time control register(cintc). the resulting integration time is expressed as; integration time = (cintr - 1) * (1 line time) + (cintc +110) * (dclk period) where cintr = 1 to { wrd / (subsr+1) + vblank }, case of ( 1<= cintr <= {wrd / (subsr+1) + vblank -1} ) 0 <= cintc <= { wcw / (subsc+1) + hblank -44 }. case of ( cintr = { wrd / (subsr+1) + vblank }, 0 <= cintc <= { wcw / (subsc+1) + hblank -205} 1-8. single frame capture mode(sfcm) integration time control to capture a still image, sfcm should be set by single frame capture enable register( sfcen ). there are two types of integration mode implement ed. in the rolling shutter mode ( sfcim = 0 ), the integration time is controlled by sfcm integration time register ( sint ). the light integration period for each rows progresses with reading rows. the integration time is expressed as : integration time = sint * (1 line time) in the mechanical shutter mode ( sfcim = 1 ), the integration time for all rows is the period during which the external input signal, strb is active. after strb gets inactivated, the external mechanical shutter should shut off incident light on image sensor, and t hen, the data readout sequence starts.
1/4 inch vga cmos image sensor S5K437CX 21 2. analog to digital converter ( adc) the image sensor has an on-chip adc. two-channel colu mn parallel adc scheme is used for separated color channel gain and offset control. 2-1. adc resolution the default value of adc resolution is 10bit and can be changed to 8-bit or 9-bit depending on the adc resolution control register ( adcres ). lowering adc resolution reduces the required minimum line time. when the number of effective output bits is reduced, upper n-bits of output ports ar e valid and lower bits always have the value of '0'. 2-2. correlated double sampling (cds) the analog output signal of each pixel has some temporal random noise and fixed pattern noise caused by the pixel reset action and the in-pixel amplifier offset devia tion respectively. to eliminate those noise components, a correlated double sampling(cds) circuit should be used befor e converting the mode to digital. the output signal is sampled twice - one for the reset level and one for the actual signal level sampling. 2-3. programmable gain and offset control you can control the gain of individual colo r channel on the programmable gain control registers (pgcr, pgcg1, pgcg2, pgcb ) and offset on offset control registers ( offsr, offsg1, offsg2, offsb ). if the color channel separation mode is disabled ( ccsm=0 ), pgcg1 and offsg1 change the gains and offsets fo r all channels. as the value increases on the gain control register, the adc c onversion input range decreases and the gain increases as shown in the following equation: 0 5 10 15 20 25 30 35 40 45 0 163248648096112128 programmable gain control channel gain (db) 1 2 3 4 5 6 7 8 9 10 0 16 32 48 64 80 96 112 128 programmable gain control relative channel gain channel gain = 128 / (128 ? programmable gain control register value[6:0]) figure 6. relative channel gain r g1 r g1 g2 b g2 b r g1 r g1 g2 b g2 b
1/4 inch vga cmos image sensor S5K437CX 22 2-4. quadrisectional global gain control you can control the global gain to change the gain for a ll color channels on the global gain control registers ( sgg1 , sgg2 , sgg3 , sgg4 ). the global gain control register is compos ed of four register groups and each register value decides the gain for each quarter section of output code level. global gain = ( sgg [3:0]+1) / 8 -20 -15 -10 -5 0 5 10 0 2 4 6 8 10 12 14 16 programmable gain control glabal gain (db) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0246810121416 programmable gain control relative global gain figure 7. relative global gain the adc gain is dependent on mclk frequency (not on dclk frequency) and adc resolution. the default global gain is set for typical mclk frequency (24.54mhz) and 10-bit adc. w hen the frequency and adc resolution are changed, the global gain should be changed in order that t he resulting gain should be maintained over unity to ensure appropriate adc conversion range. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01234 56789101112131415161718192021222324252627282930 mclk frequency (mhz) minimum glabal gain 10-bit adc resolution 9-bit adc resolution 8-bit adc resolution figure 8. recommended minimum global gain control value
1/4 inch vga cmos image sensor S5K437CX 23 by appropriately programming these four register values, you can acquire different output resolutions depending on the signal and can increase the intra-scene dynamic range by 16 times. in another application, the sectional global gain control can be used as a rough gamma correction with four sectional linear approximation curves as shown in figure 9. 255 0 511 767 1023 adc output code at 10-bit resolution sgg1=1111b sgg2=0111b sgg3=0011b sgg4=0000b adc input signal sgg1=0111b sgg2=0111b sgg3=0111b sgg4=0111b sgg1 sgg2 sgg3 sgg4 figure 9. quadrisectional global gain control 3. post processing 3-1. auto dark level compensation(adlc) the dark level of image sensor means the average output level without illumination. it includes pixel output caused by leakage current of the photodiodes and adc offse t. to compensate the dark level, the output level of optical black(ob) pixels should be in a good reference va lue. auto dark level compensation has 4 operating modes. adlc mode a only works for (adlc_length +1) fr ame time. adlc mode b only works when the change of shutter values is detected at the start of each frame. adlc mode c only works when the change of channel gain values is detected at the start of eac h frame. adlc mode d works always when this register is set to high. when adlc mode is activated, the image sens or detects the ob pixel level, opti onally 512x2 or 128x8, at the start of the enabled frame, and analog-to-digital conversion range is sh ifted to compensate the dark level for that frame. so, the resulting output data of that frame will be almost zero under dark state. you can select the dark level which is not zero on the adc offset regi ster (adcoffs). the lower 7-bit val ue represents the offset value in output code for compensation and the msb shows whether the offset is positive (adc offs[7]=0) or negative (adcoffs[7]=1). when not in auto dar k level compensation mode, the adcoffs [7:0] act as a output code value to subtract the output image data. please not e that all the 8-bit data are used for an offset value without a sign bit. the resulting adlc value is expressed as; adlc current = * (ob old + ob new ) + * adlc old ( is set by register feedback_gain_a , is set by register feedback_gain_b)
1/4 inch vga cmos image sensor S5K437CX 24 3-2. bad pixel replacement if the bad pixel replacement register ( bprm ) is disabled, the image sensor c hecks, with the preset threshold value ( pthresh ), if the image data is less or greater than horiz ontally neighboring pixels in same color channel. if satisfied, the output of the pixel is replaced by the averaged value of t he neighboring two pixels. the detectable defective pixels are rare and the bad pixel replacement ac tion can remove the defective image effectively. but it reduces the line resolution in the horizontal direction. 4. i 2 c serial interface i 2 c is an industry standard serial interface. i 2 c contains a serial two-wire half duplex interface that features bi- directional operation, master or slave mode. the general sda and scl are the bi-directional data and clock pins, respectively. these pins are open-drai n type ports and will require a pull-up re sistor to vdd. the image sensor operates in the salve mode only and the scl is input only. i 2 c bus interface is composed of following parts : start signal, 7-bit slave device address (0010001b) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8-bit data tr ansfer followed by an acknowledgement signal and stop signal. the sda bus line may only be changed while scl is low. the data on the sda bus line is valid on the high-to-low transition of scl . sda start d7 scl i 2 c bus address i2c register address write ack ack sda scl d7 data to write stop ack "0" "0" "1" "0" "0" "0" "1" d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 figure 10. i 2 c bus write cycle
1/4 inch vga cmos image sensor S5K437CX 25 sda start d7 scl "0" i 2 c bus address i 2 c register address write ack ack stop x sda re-start d7 scl "0" i 2 c bus address data to be read read ack ack "0" 1 "0" "0" "0" 1 d6 d5 d4 d3 d2 d1 d0 "0" "1" "0" "0" "0" "1" d6 d5 d4 d3 d2 d1 d0 figure 11. i 2 c bus read cycle
1/4 inch vga cmos image sensor S5K437CX 26 timing chart vertical timing diagram continuous frame capture mode (default case) hsync wrd (480 rows) 1 frame = wrd + vblank (525 rows ) wrp (14th row) vsync vswd (1row) data vblank (45rows) (delayed vertical sync case) hsync 1 frame = wrd + vblank (525 rows) vsync vsstrt data 2 rows vswd 2 rows
1/4 inch vga cmos image sensor S5K437CX 27 (vertical data valid mode case) vsdisp = 1 hsync (hsdisp=0) wrd vsync data vblank hsync (hsdisp=1)
1/4 inch vga cmos image sensor S5K437CX 28 horizontal timing diagram (default case) wcw ( 640 columns ) 1 row = wcw + hblank ( 780columns) hswd (32 dclk) hblank (140columns) hsync vsync data dclk 10 dclk wcp (14th column) (delayed horizontal sync case) wcw 1 row = wcw + hblank hsstrt hsync vsync data dclk hswd 42 dclk 42 dclk
1/4 inch vga cmos image sensor S5K437CX 29 (horizontal data valid mode case ) hsdisp = 1 wcw hsync vsync data dclk 42 dclk hblank
1/4 inch vga cmos image sensor S5K437CX 30 48clcc package dimension (test only) 0.51 + 0.08 r 0.15 4 corners 48 1 1.016 + 0.18 11.176 + 0.13 1.016 + 0.08 center of image area (x = + 0.50 + 0.15, y = 0.00 + 0.15 from package center) max. chip rotation = + 1.5 degree max. chip tilt = 0.05mm center of image area (x=+0.50 + 0.15, y= 0.00 + 0.15 from package center) max. chip rotation = + 1.5 degree max. chip tilt = 0.05mm top view side view bottom view 18 42 31 14.22sq + 0.30/-0.13 19 30 643 48 1 7 x 0.55 + 0.05 glass 1.65 + 0.18
1/4 inch vga cmos image sensor S5K437CX 31
1/4 inch vga cmos image sensor S5K437CX 32 notes ? 2004 samsung electronics all rights reserved. no part of this publication may be r eproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, record ing, or otherwise, without the prior written consent of samsung electronics. samsung electronics co., ltd. san #24 nongseo-ri, giheung-eup yongin-city, gyeonggi-do, korea c.p.o. box #37, suwon 449-900 homepage: www.samsungsemi.com

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